Read:

Following are the details: : Start signal SCL SDA High High High Low The Start signal is HIGH to LOW transition on the SDA line when SCL is HIGH. : Write Slave Address: 58h or 5Ch : Read Slave Address: 59h or 5Dh
SDA
SDA Data bit [1] or NA SCL
SDA Data bit [0] or A SCL
: Value of the AL250/251 register index. : Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) for the AL250/251 (slave) to pull down the SDA line during the acknowledge clock pulse. : Not Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) during the acknowledge clock pulse, but the AL250/251 does not pull it down during this stage.
START bit [S] SCL
STOP bit [P] SCL
SDA Not significant SCL
AL250-15 I2C drawing
: Data byte write to or read from the register index. In read operation, the host must release the SDA line (high) before the first clock pulse is transmitted to the AL250.
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: Stop signal SCL SDA High Low High High The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH.
Suppose data F0h is to be written to register 0Fh using write slave address 58h, the timing is as follows:
Start
Slave addr = 58h
Ack
Index = 0Fh
Ack
Data = F0h
Ack Stop
SDA SCL
AL250-24 I2C Write timing
Suppose data is to be read from register 55h using read slave address 59h, the timing is as follows:
Start
Slave addr = 58h
Ack
Index = 55h
Ack
Stop Read slave addr = 59h NAck Start Ack Data read cycle Stop
SDA SCL
AL250-25 I2C Read timing
6.9 Video Decoding
A video decoder (video input processor) is needed with the AL250/251 for S-video or composite video processing. Please note that the AL250/251 works only with line-locked video decoders. There are a number of video decoders available in the market; following is a selection chart. For detailed information, please consult with the decoder vendors or their distributors directly. The attached information is believed to be accurate but not guaranteed.
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Decoder SAA 7110 SAA 7111 SAA 7112 KS0127 VPC3211B
Vendor Philips Philips Philips Samsung ITT
Line locked V V V V V
NTSC/ PAL V V V V V
RGB565
CCIR 601 V V V V
Square Pixel V
Closed Caption
Tele text
V V V
V
V V
More information on the AL250/251 functionality can be found in the Register Definition section.
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7.0 Electrical Characteristics
7.1 Recommended Operating Conditions
Parameter VDD TAMB Supply Voltage Ambient Operating Temperature Min +3.0 0 Max +5.5 +70 Unit V C
7.2 Characteristics
Parameter IDD P VIH VIL VOH VOL IO Supply current Power consumption Hi-level input voltage Lo-level input voltage Hi-level output voltage Lo-level output voltage Output current, data Output current, GHREF Output current, GHS, GVS ILI Ci CK2 tiS tiH tr tf tdCK CL toH tPD Input leakage current Input pin capacitance Duty factor (tCK2H/tCK2) Input data set-up time Input data hold time Input rise time Input fall time VCLK to VCLKx2 delay Digital output load cap. Output hold time Propagation delay CL = 15pF CL = 40pF Vi = 0.6 to 2.6V Vi = 2.6 to 0.6V -0.5VJuly 28, 1999
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The input and output timing diagrams are as follows:
tCK2
VCLKX2
tCK2H tCK2L tf tr
tCK
VCLK
tdCK tf tr
tiS
tiH
VDIN
AL250-22 Input timing
tCK2
VCLKX2
tCK2H tCK2L tf tr
tPD
DO
toH
AL250-23 Output timing
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8.0 AL250/251 Register Definition
The AL250/251 is powered up to a default state depending on the hardware mode-setting pins. Hardware configuration pins are disabled by setting SoftConfig (bit 4 of register 03h) to one, and configurations are decided by the values of register 02h which is software programmable. The following is the summary of the AL250/251 control registers
Register COMPANYID REVISION BOARDCONFIG GENERAL FAMILY CONTROL STATUS BORDERRED BORDERGREEN BORDERBLUE LUTOSDCONTROL LUTOSDINDEX LUTOSDDATA OVERLAYCTRL OVL1RED OVL1GREEN OVL1BLUE OVL2RED OVL2GREEN OVL2BLUE OVL3RED OVL3GREEN OVL3BLUE OSD1HSTART OSD2HSTART HDESTART HDEEND Addr. 00h 01h 02h 03h 04h 08h 09h 0Ch 0Dh 0Eh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h 00h 00h 00h FFh FFh FFh 00h FFh 00h 00h 00h 00h 00h 00h R/W R R R/W R/W R R/W R R/W R/W R/W R/W W Default 46h 00h ?? 00h 25h 00h ?? 00h 00h 00h 00h 00h Company ID Revision number Board configuration General control Chip family number Control register Status register Border color, red channel Border color, green channel Border color, blue channel LUT/OSD control LUT/OSD index Reserved LUT/OSD data Overlay Effect Control Overlay color 1, red channel Overlay color 1, green channel Overlay color 1, blue channel Overlay color 2, red channel Overlay color 2, green channel Overlay color 2, blue channel Overlay color 3, red channel Overlay color 3, green channel Overlay color 3, blue channel On Screen Display bitmap 1 horizontal start On Screen Display bitmap 2 horizontal start Horizontal capture start Horizontal capture end Function
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HSYNCSTART HSYNCEND HTOTAL(1) VDESTART VDEEND VSYNCSTART VSYNCEND HTOTAL(2) TEST HBORDERSTART HBORDEREND VBORDERSTART VBORDEREND OSDVSTART
22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Horizontal sync. start Horizontal sync. end Horizontal total high, bit<10:3> Vertical capture start Vertical capture end Vertical sync. start Vertical sync. end Horizontal total low, bit<2:1> Test register(Reserved) Horizontal border color start Horizontal border color end Vertical border color start Vertical border color end On Screen Display bitmap 1 and 2 vertical start
8.1 Register Description
00h: Company ID (R) [COMPANYID] CompanyId <7:0> Company ID (46h) Revision (R) [REVISION] Revision <7:0>
01h:
Revision number
02h:
Board Configuration (R/W) [BOARDCONFIG] If SoftConfig (Reg.#03h<4>) = 0, the hardware configuration pins values are read. If SoftConfig (Reg.#03h<4>) = 1, the software configuration register values are read STD <1:0> Input video standard 00 NTSC input 01 PAL input 10 Automatic standard detection 11 Reserved for analog testing InType <2> Input video format 0 YUV422 1 RGB565 uvflip <3> if 1, flip UV Square <4> 0 CCIR 1 Square pixel General (R/W) [GENERAL]
03h:
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SoftConfig
<0> <3:1> <4> <7:5>
Reserved Reserved Enable configuration defined by software configuration register 02h. Please refer to Reg.#02h Reserved
04h:
Chip Family (R) [FAMILY] Family <7:0> 25h, AL250/251 series Control (R/W) [CONTROL] <0> Reserved InVsPol <1> Input vsync polarity 0 negative polarity 1 positive polarity InHsPol <2> Input hsync polarity 0 negative polarity 1 positive polarity Softtime <3> Enable H & V adjustment (register 20h to 29h) OutHsPol <4> Output hsync polarity 0 negative polarity 1 positive polarity OutVsPol <5> Output vsync polarity 0 negative polarity 1 positive polarity OutFormat <7> Output video format 0 16-bit RGB 565 1 CCIR YUV422 Chip Status (R) [STATUS] PalDetected <0> VidVs <1> HRef <2> VidHs <3> GVde <4> OvlCtrl0 <5> OvlCtrl1 <6>
08h:
09h:
PAL detected External vsync External href External hsync Internal gvde signal External ovlctrl0 External ovlctrl1
Note: If PalDetected is always 1, the input mode is PAL. If PalDetected is not always 1, then the input mode is NTSC. 0Ch: Border Color Red (R/W) [BORDERRED] BorderRed <7:0> Border color, red component Border Color Green (R/W) [BORDERGREEN] BorderGreen <7:0> Border color, green component Border Color Blue (R/W) [BORDERBLUE]
0Dh:
0Eh:
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BorderBlue 10h:
<7:0>
Border color, blue component
LUT/OSD Control (R/W) 0x10 [LUTOSDCONTROL] LutOsdWSel <1:0> LUT/OSD table write select 00 enable LUT-red table write 01 enable LUT-green table write 10 enable LUT-blue table write 11 enable OSD (On Screen Display) bitmap write RLutEn <2> LUT-red enable 0 bypass red LUT 1 enable red LUT GLutEn <3> LUT-green enable 0 bypass green LUT 1 enable green LUT BLutEn <4> LUT-blue enable 0 bypass blue LUT 1 enable blue LUT BitMap1En <6> Bitmap 1 enable 0 hide bitmap 1 1 show bitmap 1 BitMap2En <7> Bitmap 2 enable 0 hide bitmap 2 1 show bitmap 2 LUT/OSD Index (W) [LUTOSDINDEX] LutOsdIndex <7:0> LUT/OSD index LUT/OSD Data (W) [LUTOSDDATA] LutOsdData <7:0> LUT/OSD data
11h:
13h:
To program the contents of LUT/OSD, first set Reg.#10h, bit<1:0>, then repeat writing index value to Reg.#11h, and data value to Reg.#13h. 14h: Overlay Control (R/W) [OVERLAYCTRL] OvlLogic1 <1:0> Overlay logic operation between video and overlay color 1 when overlay key = "01" 00 select overlay color 1 01 video AND overlay color 1 10 video OR overlay color 1 11 video XOR overlay color 1 OvlLogic2 <3:2> Overlay logic operation between video and overlay color 2 when overlay key = "10" 00 select overlay color 2 01 video AND overlay color 2 10 video OR overlay color 2 11 video XOR overlay color 2
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OvlLogic3
<5:4>
OvlLut
<7>
Overlay logic operation between video and overlay color 3 when overlay key = "11" 00 select overlay color 3 01 video AND overlay color 3 10 video OR overlay color 3 11 video XOR overlay color 3 If 1, video will go through LUTs when ovlkey pins are "11" and OvlLogic3 settings are ignored.
15h:
Overlay Color 1 Red (R/W) [OVL1RED] Overlay1Red <7:0> Overlay 1 color red component Overlay Color 1 Green (R/W) [OVL1GREEN] Overlay1Green <7:0> Overlay 1 color green component Overlay Color 1 Blue (R/W) [OVL1BLUE] Overlay1Blue <7:0> Overlay 1 color blue component Default RGB value for overlay 1 is: (R, G, B) = (0, 0, 255), blue Overlay Color 2 Red (R/W) [OVL2RED] Overlay2Red <7:0> Overlay 1 color red component Overlay Color 2 Green (R/W) [OVL2GREEN] Overlay2Green <7:0> Overlay 1 color green component Overlay Color 2 Blue (R/W) [OVL2BLUE] Overlay2Blue <7:0> Overlay 1 color blue component Default RGB value for overlay 2 is: (R, G, B) = (255, 255, 0), yellow Overlay Color 3 Red (R/W) [OVL3RED] Overlay3Red <7:0> Overlay 3 color red component Overlay Color 3 Green (R/W) [OVL3GREEN] Overlay3Green <7:0> Overlay 3 color green component Overlay Color 3 Blue (R/W) [OVL3BLUE] Overlay3Blue <7:0> Overlay 3 color blue component Default RGB value for overlay 3 is: (R, G, B) = (255, 0, 0), red On-Screen Display 1 (OSD1) Horizontal Start (R/W) [OSD1HSTART] Osd1HStart <7:3> On Screen Display bitmap 1 horizontal start. (unit: 64 pixels) On-Screen Display 2 (OSD2) Horizontal Start (R/W) [OSD2HSTART] Osd2HStart <7:3> On Screen Display bitmap 2 horizontal start. (unit: 64 pixels) On Screen Display (OSD) Vertical Start (R/W) [OSDVSTART]
16h:
17h:
18h:
19h:
1Ah:
1Bh:
1Ch:
1Dh:
1Eh:
1Fh:
2Fh:
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On Screen Display bitmap 1 and 2 vertical start. (unit: 64 lines) MeshColor <1> Mesh color select 0 gray mesh 1 color 3 mesh MeshEn <0> Mesh background enable 0 No mesh 1 Enable mesh background To display the OSD correctly, make sure the horizontal start does not locate between horizontal sync start and horizontal sync end, and vertical start does not locate between vertical sync start and vertical sync end. Reg.#20h to #29h define the video capture control timing. 20h: Horizontal Capture Start (R/W) [HDESTART] HDEStart <7:0> Horizontal capture start. (unit: 8 pixels) Horizontal Capture End (R/W) [HDEEND] HDEEnd <7:0> Horizontal capture end. (unit: 8 pixels) Horizontal Sync Start (R/W) [HSYNCSTART] HSyncStart <7:0> Horizontal sync start. (unit: 8 pixels) Horizontal Sync End (R/W) [HSYNCEND] HSyncEnd <7:0> Horizontal sync end. (unit: 8 pixels) Horizontal Total High (R/W) [HTOTAL1] HTotal10_3 <7:0> Bit 10 to bit 3 of horizontal total Bit 2 to bit 1 are defined in Reg.#29h<1:0> Vertical Capture Start (R/W) [VDESTART] VDEStart <7:0> Vertical capture start. (unit: 4 lines) Vertical Capture End (R/W) [VDEEND] VDEEnd <7:0> Vertical capture end. (unit: 4 lines) Vertical Sync Start (R/W) [VSYNCSTART] VSyncStart <7:0> Vertical sync start. (unit: 4 lines) Vertical Sync End (R/W) [VSYNCEND] VSyncEnd <7:0> Vertical sync end. (unit: 4 lines)
OsdVstart
<7:4>
21h:
22h:
23h:
24h:
25h:
26h:
27h:
28h:
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29h:
Horizontal Total Low (R/W) [HTOTAL2] <7:2> Reserved HTotal2_1 <1:0> Bit 2 to bit 1 of horizontal total, htotal bit 0 = 0 Test (R/W) [TEST] testIn <7> testOut <6> testOvl <5:4>
2Ah:
<3:0> 2Bh:
Feed RGB value from 0x15, 0x16, 0x17 registers to the input Feed RGB value from 0x15, 0x16, 0x17 registers to the output 00, use hardware overlay key 01, set overlay key value to 01 10, set overlay key value to 10 11, set overlay key value to 11 Reserved
Horizontal Blank Start (R/W) [HBLANKSTART] HBlankStart <7:0> Horizontal blanking start. (unit: 8 pixels) Horizontal Blank End (R/W) [HBLANKEND] HBlankEnd <7:0> Horizontal blanking end. (unit: 8 pixels) Vertical Blank Start (R/W) [VBLANKSTART] VBlankStart <7:0> Vertical blanking start. (unit: 4 lines) Vertical Blank End (R/W) [VBLANKEND] VBlankStart <7:0> Vertical blanking end. (unit: 4 lines)
2Ch:
2Dh:
2Eh:
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9.0 Board Design and Layout Considerations
The AL250/251 contains both precision analog and high-speed digital circuitry. Noise coupling from digital circuits to analog circuits may result in poor video quality. The layout should be optimized for lowest noise on the power and ground planes by shielding the digital circuitry and providing good decoupling. It is recommended to place the AL250/251 chip close to the VGA output connector, and the video decoder close to the analog video input connectors if applicable.
9.1 Grounding
Analog and digital circuits are separated within the AL250/251 chip. To minimize system noise and prevent digital system noise from entering the analog portion, a common ground plane for all devices, including the AL250/251 is recommended. All the connections to the ground plane should have very short leads. The ground plane should be solid, not cross-hatched.
9.2 Power Planes and Power Supply Decoupling
The analog portion of the AL250/251 and any associated analog circuitry should have their own power plane, referred to as the analog power plane (AVDD). The analog power plane should be connected to the digital power plane (DVDD) at a single point through a low resistance ferrite bead. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all of the AL250/251 analog power pins and relevant analog circuitry. Power supply connection pins should be individually decoupled. For best results, use 0.1F ceramic chip capacitors. Lead lengths should be minimized. The power pins should be connected to the bypass capacitors before being connected to the power planes. 22F capacitors should also be used between the AL250/251 power planes and the ground planes to control low-frequency power ripple.
9.3 Digital Signal and Clock Interconnect
Digital signals to the AL250/251 should be isolated as much as possible from the analog outputs and other analog circuitry. The high frequency clock reference or crystal should be handled carefully. Jitter and noise on the clock will degrade the video performance. Keep the clock paths to the decoder as short as possible to reduce noise pickup.
9.4 Analog Signal Interconnect
The AL250/251 should be located closely to the output connectors to minimize noise and reflections. Keep the critical analog traces as short and wide (20~30 mil) as possible. Digital signals, especially pixel clocks and data signals should not overlap any of the analog signal circuitry and should be kept as far apart as possible. The AL250/251 and the decoder IC should have no inputs left floating.
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10.0 Mechanical Drawing
AL250: 20mm x 14mm 64-pin QFP package
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AL251: 20mm x 14mm 80-pin QFP package
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11.0 Power Consumption
The AL250/251 works at both 5V and 3.3V. The following table shows the current consumption of the AL250/251 itself and that of the whole EVB with power supply at single 5V, or 5V and 3.3V mixed (3.3V for the AL250/251 only). +5V AL250/251 chip AL250 EVB 92 mA (typ.) 280 mA (typ.) +3.3V for AL250 +5V for the rest 55 mA (typ.) 140 mA (typ.)
Please be reminded that when lower power supply is used, the pull-down resistance to the RSET pin has to be adjusted to compensate accordingly. The lower the supply voltage is, the lower the pulldown resistance has to be. The ideal resistance value can be achieved by adjusting the RGB output to be 0.7V peak-to-peak or higher to obtain better output brightness and contrast.
For more information about the AL250/251 or other AverLogic products, please contact your local authorized representatives, visit our website, or contact us directly.
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CONTACT INFORMATION
Averlogic Technologies Corp. 4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan Tel: +886 2-27915050 Fax: +886 2-27912132 E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw
Averlogic Technologies, Inc. 90 Great Oaks Blvd. #204, San Jose, CA 95119 USA Tel: 1 408 361-0400 Fax: 1 408 361-0404 E-mail: sales@averlogic.com URL: http://www.averlogic.com